The invention relates to an AGC (Automatic Gain Control) circuit which is used for a magnetic recording and reproducing apparatus or the like and controls an amplitude value in accordance with a set value.
In a magnetic recording/reproducing apparatus to record and reproduce signal information as a magnetic signal onto/from a magnetic recording medium, an amplitude level of the signal which was read out in the data reproducing mode fluctuates due to a difference of the inner and outer rims of the recording medium or the like. An AGC circuit executes a control so as to keep the fluctuation of the signal amplitude to a constant value. FIG. 8 is a constructional diagram of a reading system signal processing circuit of the magnetic recording/reproducing apparatus. FIG. 9 is a block diagram of the AGC circuit. FIG. 10 is a constructional diagram of a VGA controller in the AGC circuit. A conventional technique will now be described with reference to the diagrams.
In FIG. 8, the reading system processing circuit of the magnetic recording/reproducing apparatus comprises: a magnetic recording medium 1 to which a magnetic signal is recorded; a magnetic head 2 to the magnetic signal on the magnetic recording medium to an electric signal 101; an R/W (read/write) amplifier 3 to amplify the electric signal reproduced; an AGC circuit 4 to control an amplitude value of an analog signal 102 amplified; a timing recovery circuit 5 to recover a timing clock signal 104 which is necessary to identify as data from a reproduction signal 103; a decoder 6 to decode the data by the read data and the timing clock; a controller 7 for receiving decoded reproduction data 105 and a timing clock 106 and converting a format of the data and also controlling a data transfer to a host; and a microcomputer 8 to control the whole circuit. In the case where a decoder of Viterbi or the like which inputs a digital value is used as a decoder 6 in FIG. 8, it is desirable that the AGC circuit 4 and the timing recovery circuit 5 are also feedback controlled by using the digital value as an input signal 104 to the decoder when considering the performance. A construction of the AGC circuit of a conventional digital control (analog drive) type is shown in FIG. 9.
As shown in FIG. 9, the conventional AGC circuit 4 comprises: a VGA (Variable Gain Amplifier) 11 to change an amplification gain by a control signal 201; an equalizer 12 to equalize an output 202 of the VGA; an A/D converter 13 to quantize an equalizer output 203; a (1+D) block 14 to execute a band-limiting of a quantization output 204 for a PR4 (Partial-Response Class-IV) process; a VGA controller 15 for detecting an error with the set amplitude from the signal after the (1+D) block and producing an error signal 205; a D/A converter 16 to convert the error signal 205 to the analog value; a multiplier 17 to multiply a D/A converter output 206 by a predetermined coefficient; and an integrator 18 for integrating a multiplier output 207 and producing the control signal 201 of the VGA.
FIG. 10 shows a construction of the VGA controller 15 to form a control signal for driving an analog section such as a VGA or the like on the basis of the amplitude information. In FIG. 10, the VGA controller 15 comprises: a discriminator 21 for judging the level of the input signal 103 and producing a judgment signal 301; a multiplier 22 to multiply the input signal 103 and the judgment signal 301; a multiplexer 23 for selecting one of the set amplitude value A and 0 on the basis of the judgment signal 301 and outputting; a subtracter 24 for subtracting an output 303 of the multiplexer from a multiplier output 302 thereby forming a difference signal 304; a delay 25 to delay the difference signal value 304 by the control clock 104 by one clock; and an adder 26 to add the difference signal 304 and a difference signal 305 as an output of the delay which is preceding by one sample, thereby forming the error signal 205.
The input signal 102 of the AGC circuit will now be described with reference to FIG. 11 and the operation of the conventional AGC circuit will be explained with reference to FIGS. 12 and 13. A sector format of the magnetic recording medium is shown in FIG. 11. Timing charts for the operation of the conventional AGC circuit are shown in FIGS. 12 and 13.
In FIG. 11, a sector which is one group of recording information in a hard disk drive or the like comprises: a GAP 41 which is arranged between sectors and compensates a speed fluctuation amount; an ID 43 in which an address of the sector is written; a sync signal section SYNC 42 to form a timing clock which is necessary to read the ID 43; a GAP 44 which is arranged between the ID and the SYNC and compensates the speed fluctuation amount; an SYNC 45 to form a timing clock which is necessary to read DATA 46 in a manner similar to the SYNC 42; and the DATA 46 to which actual information is stored. Since the address and data are written respectively in the ID 43 and the DATA section 46, the signals which are read out from them have a random pattern. The SYNC 42 has a predetermined regular pattern so that the timing recovery circuit 5 obtains a synchronization on the basis of the pattern. That is, although the DATA 46 can obtain a random value of {1, 0, -1} at the sampling point, in the regions of the SYNC 45, for example, in case of executing the PR4 process, a regular bit sequence of {1, 0, -1, 0, . . . } is obtained. After the (1+D) process was executed, the signal is set to a bit sequence of {1, 1, -1, 1, . . . }.
The operation of the AGC circuit shown in Fig. 9 will now be explained. First, a case where the random data in the ID 43 and DATA section 46 in the sector is supplied to the AGC circuit will be described.
The VGA output signal 202 which was amplified by gain times through the VGA 11 is equalized by the equalizer 12 and after that it is quantized by the A/D converter 13. After that, in the (1+D) block 14, the value of one sample before is added to the quantized signal to execute a PR process, thereby forming the VGA controller input signal 103. The VGA controller input signal 103 is supplied to the decoder 6 and also to the VGA controller 15. The VGA controller 15 shown in Fig. 10 receives the input signal 103 (V103) and first forms the judgment signal (V301) by the discriminator 21 under the following judging conditions. ##EQU1## where, V103: a discriminator input, V301: a discriminator output, and A: an AGC set amplitude value
The VGA controller input signal V103 is multiplied by the judgment signal V301 of the discriminator output, thereby setting the signal to the absolute value. The data in which the judgment signal V301 corresponds to "0" is multiplied by "0" and such data is not used as information to set an amplitude. After that, the multiplexer 23 selects 0 when the discriminator output V103 is equal to 0 and selects the set amplitude value A when the discriminator output V103 is equal to 1 or -1. The subtracter 24 forms the difference signal 304 by subtracting the value selected by the multiplexer 23 from the multiplier output signal 302. The difference signal 304 is filtered by the (1+D) operation by the delay 25 and the adder 26, thereby forming the error signal 205. The D/A converter 16 shown in FIG. 9 converts the error signal 205 into the analog value. After that, the analog value is multiplied by a coefficient to determine a loop gain of the AGC loop by the multiplier 17 and the value is subsequently integrated by the integrator 18. The result is used as a control signal 201 of the VGA.
By such a feedback control mentioned above, when the amplitude of the VGA controller input signal is larger than the set amplitude value, the absolute value of the control signal 201 is reduced, thereby decreasing the gain of the VGA. On the other hand, when the amplitude of the VGA controller input signal is smaller than the set amplitude value, the gain is increased. The amplitude of the VGA controller input signal at the sampling point is equalized to the set amplitude value finally. A similar operation is also executed in the case of regular data in the SYNC shown in FIG. 13. In the AGC circuit, the sampling clock recovered by the timing recovery circuit 5 is used as a sampling clock which is used for the A/D converter 13, (1+D) block 14, and VGA controller 15.
There is the technique disclosed in JP-A-61-129913 as a conventional technique.